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30PCS AT24C02 2-wire serial eeprom
http://pdf.dzsc.com/6A-/AT24C16A-10PI-2.7.pdf
Low-voltage and Standard-voltage Operation
Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
Schmitt Trigger, Filtered Inputs for Noise Suppression
100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
Self-timed Write Cycle (5 ms max)
Endurance: 1 Million Write Cycles
Automotive Grade and Lead-free/Halogen-free Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23,
8-lead TSSOP and 8-ball dBGA2 Packages
Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP,
8-lead JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-
lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface.
In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to
Operating Temperature.................................. 55 C to +125 C *NOTICE: Stresses beyond those listed
Maximum Ratings may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
Storage Temperature ..................................... 65 C to +150 C
with Respect to Ground .................................... 1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
open-drain driven and may be wire-ORed with any number of other open-drain or opencollector
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that are hard wired for the AT24C01A and the AT24C02. As many as
eight 1K/2K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K
devices may be addressed on a single bus system. The A0 pin is a no connect.
The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no
The AT24C16A does not use the device address pins, which limits the number of
devices on a single bus to one. The A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal Read/Write
operations when connected to ground (GND). When the Write Protect pin is connected
to VCC, the write protection feature is enabled and operates as shown in Table 2.
Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,
the 1K requires a 7-bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.
AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,
the 4K requires a 9-bit data word address for random word addressing.
AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each,
the 8K requires a 10-bit data word address for random word addressing.
AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes
each, the 16K requires an 11-bit data word address for random word addressing.
24C01A 24C02 24C04 24C08A 24C16A
At GND Normal Read/Write Operations
Note: 1. This parameter is characterized and is not 100% tested.
Note: 1. VIL min and VIH max are reference only and are not tested.
Applicable over recommended operating range from TA = 25 C, f = 1.0 MHz, VCC = +1.8V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
Applicable over recommended operating range from: TAI = 40 C to +85 C, VCC = +1.8V to +5.5V, VCC = +1.8V to
Symbol Parameter Test Condition Min Typ Max Units
ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA
ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA
ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 A
ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 1.4 4.0 A
ISB3 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 A
ISB4 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 A
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 A
ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 A
VIL Input Low Level(1) 0.6 VCC x 0.3 V
VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
Note: 1. This parameter is characterized.
Applicable over recommended operating range from TAI = 40 C to +85 C, VCC = +1.8V to +5.5V, VCC = +2.7V to
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
fSCL Clock Frequency, SCL 100 400 kHz
tLOW Clock Pulse Width Low 4.7 1.2 s
tHIGH Clock Pulse Width High 4.0 0.6 s
tI Noise Suppression Time(1) 100 50 ns
tAA Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 s
Time the bus must be free before
a new transmission can start(1) 4.7 1.2 s
tHD.STA Start Hold Time 4.0 0.6 s
tSU.STA Start Setup Time 4.7 0.6 s
tHD.DAT Data In Hold Time 0 0 s
tSU.DAT Data In Setup Time 200 100 ns
tR Inputs Rise Time(1) 1.0 0.3 s
tF Inputs Fall Time(1) 300 300 ns
tSU.STO Stop Setup Time 4.7 0.6 s
tDH Data Out Hold Time 100 50 ns
Endurance(1) 5.0V, 25 C, Byte Mode 1M 1M
Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
2. Look for SDA high in each cycle while SCL is high.
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O
Figure 3. SCL: Serial Clock, SDA: Serial Data I/O
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the
Figure 5. Start and Stop Definition
Device Addressing The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word
following a start condition to enable the chip for a read or write operation (refer to Figure
The device address word consists of a mandatory one, zero sequence for the first four
most significant bits as shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.
These 3 bits must compare to their corresponding hard-wired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a
memory page address bit. The two device address bits must compare to their corresponding
hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for
memory page addressing. The A2 bit must compare to its corresponding hard-wired
input pin. The A1 and A0 pins are no connect.
The 16K does not use any device address bits but instead the 3 bits are used for memory
page addressing. These page addressing bits on the 4K, 8K and 16K devices
should be considered the most significant bits of the data word address which follows.
The A0, A1 and A2 pins are no connect.
The eighth bit of the device address is the read/write operation select bit. A read operation
is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the chip will return to a standby state.
Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition.
At this time the EEPROM enters an internally timed write cycle, tWR, to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (see Figure 8 on page 11).
PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K
and 16K devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero
after each data word received. The microcontroller must terminate the page write
sequence with a stop condition (see Figure 9 on page 11).
The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally
incremented following the receipt of each data word. The higher data word address bits
are not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data
words are transmitted to the EEPROM, the data word address will roll over and previous
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero allowing the read or write sequence to continue.
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address roll
over during read is from the last byte of the last memory page to the first byte of the first page.
The address roll over during write is from the last byte of the current page to the first byte of
Once the device address with the read/write select bit set to one is clocked in and acknowledged
by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condition
RANDOM READ: A random read requires a dummy byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a following
stop condition (see Figure 11 on page 12).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random
address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will roll over and the sequential read will continue.
The sequential read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition (see Figure 12 on page 12).
Figure 10. Current Address Read
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC
2. U designates Green Package + RoHS compliant.
3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request.
AT24C01A Ordering Information(1)
Ordering Code Package Operation Range
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)
8U3-1 8-ball, die Ball Grid Away Package (dBGA2)
2.7 Low-voltage (2.7V to 5.5V)
1.8 Low-voltage (1.8V to 5.5V)
AT24C02 Ordering Information(1)
AT24C04 Ordering Information(1)
AT24C08A Ordering Information(1)
8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8Y5 8-lead, 2.00 mm x 3.00 mm Body, Dual Footprint, Non-Leaded, Miniature Array Package (MAP)
8U2-1 8-ball, die Ball Grid Array Package (dBGA2)
.2.7 Low Voltage (2.7V to 5.5V)
.1.8 Low Voltage (1.8V to 5.5V)
AT24C16A Ordering Information(1)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions,
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink
Small Outline Package (SHRINK SOT)
NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing
MO-193, Variation AB, for additional information.
2. Dimension D does not include mold flash, protrusions, or gate burrs.
Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end.
Dimension E1 does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.15 mm per side.
3. The package top may be smaller than the package bottom. Dimensions
D and E1 are determined at the outermost extremes of the plastic body
exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
4. These dimensions apply to the flat section of the lead between 0.08 mm
and 0.15 mm from the lead tip.
5. Dimension "b" does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08 mm total in excess of the "b" dimension at
maximum material condition. The Dambar cannot be located on the lower
radius of the foot. Minimum space between protrusion and an adjacent lead
shall not be less than 0.07 mm.
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
1. Dimension b is measured at the maximum solder ball diameter.
This drawing is for general information only.
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